This invention relates to methods of forming field effect transistors, and to field effect transistor circuitry.
It is desirable in transistors to be able to drive high currents. Driving high currents can enhance a transistor""s operating performance including its operating speed. In field effect transistors (FETs), current flow is primarily conducted by way of the drain-to-source current Ids. While higher drive currents can be achieved by building wider FET devices, tradeoffs are made in valuable wafer real estate. Larger devices also typically have larger capacitances which can adversely impact device performance. Also typically, a high Ids current in FET devices can result in an increased sub-threshold current leakage. It is desirable in FETs to minimize the sub-threshold current leakage. Accordingly, it is desirable to have the Ids ratio of on-state current (Ion) to off-state current (Ioff) be as high as possible. Such improves sub-threshold device leakage characteristics as well as increases the transistor""s operating speed performance.
This invention arose out of concerns associated with improving field effect transistor performance.
Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor""s gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.